1. Field of the Invention
The present invention relates to a power management architecture scheme for a central processing unit ("CPU") implemented within a computer system. More particularly, the present invention relates to an apparatus and method for controlling a CPU clock in response to certain events within the computer system.
2. Background of the Field
It is becoming a necessity for many companies to use portable and laptop computers in their daily business activities. As a result, in order to acquire market share in an expansive and competitive portable and laptop computer industry, many computer manufacturers are attempting to decrease consumer operating costs in order to make their respective computers more affordable. As a result, for economic reasons and reliability concerns, there exists an increasing need for efficient power management architecture schemes in order to conserve power supplied by limited power sources, such as, for example, batteries.
In response to the obvious need for effective power management, Intel had developed an Intel Architecture Microprocessor ("MP") 1 comprising a central processing unit ("CPU") 2, a Power Management Macro ("PMM") 3 and a bus controller 4, each of which being coupled together by an internal system bus 5, as illustrated in FIG. 1. The MP 1 was coupled to an external system bus 6, commonly an 8-bit bus, so as to enable data communications between a plurality of peripheral devices 7a-7n and both the CPU 2 and PMM 3 via the bus controller 4. The PMM 3 for the MP I provides a circuit which controls the CPU clock 8 through asserting or deasserting a STP.sub.-- CLK interrupt signal line 9. Coupled to the PMM 3 and the CPU 2, the STP.sub.-- CLK signal line 9 is an active-low interrupt signal which allows the CPU clock 8 to be controlled by the PMM 3 in response to certain events; namely, a Stop Clock event or a Stop Break event. The Stop Clock event causes the CPU clock 8 to temporarily cease operations. The Stop Break event, on the other hand, causes the CPU clock 8 to re-start.
The PMM 3 is typically a programmable power manager comprising a plurality of storage elements, such as registers, used to maintain a list of peripherals 7a-7n which are powered-on or powered-off, a list of physical addresses of such peripherals, and circuits to monitor the internal system bus 5 for certain events. As a result, the PMM 3 is programmed in accordance with the plurality of peripherals 7a-7n coupled to the external system bus 6.
However, a few distinct disadvantages are associated with the conventional power management scheme. For example, when a computer system is idle or running an application that is not computationally intensive, power was wasted because the CPU clock 8 was unnecessarily running at its highest frequency during such times. The present invention, however, proposes slow clock emulation through "clock throttling" (i.e., alternatively running and idling the CPU clock) and selective speed up of the CPU clock in response to certain system events in the Intel Architecture Microprocessor environment. Such emulation has involved thorough redesigning of the PMM. By combining slow clock emulation with conventional stop clock and re-start clock requests, the present invention offers greater power savings than realized by conventional power management because the CPU clock is stopped as often as possible, even while the system is active (but at a low level of activity). It also offers a better response time compared to the conventional schemes, because being employed for only a programmable duration, the CPU uses its maximum frequency to service critical events in the system.
Accordingly, it would be advantageous to maximize power savings with minimal impact on performance as well as to provide a power management scheme which not only allows the CPU clock to become idle, but also provides a power management scheme which controls power by selectively altering the clock speed of the CPU clock and allows the CUP to emulate any desired frequency up to its maximum frequency.